1. Field of the Invention
The present invention relates to techniques for minimizing phase error and jitter in a phased-locked loop circuit. More specifically, the present invention relates to a phase-locked loop with a charge pump that has a current compensation mechanism that substantially equalizes current flowing through a pull-up network and through a pull-down network to minimize phase error and jitter in the phase-locked loop.
2. Related Art
Advances in semiconductor fabrication technology presently make it possible to integrate large-scale systems, including tens of millions of transistors, into a single semiconductor chip. Integrating such large-scale systems onto a single semiconductor chip enables increases in the frequency at which such systems can operate, because signals between system components do not have to cross chip boundaries, and are not subject to lengthy chip-to-chip propagation delays.
Increasing the operating frequency of such systems typically involves using a phase-locked loop (PLL), which takes a low-frequency off-chip clock signal, typically from a quartz crystal, and generates a higher frequency clock signal. FIG. 1 presents a block diagram of such a PLL. It has phase/frequency detector 102, charge pump 104, loop filter 106, voltage-controlled oscillator 108, frequency divider 110, output clock frequency 112, divided clock 114, and reference clock 116.
The PLL operates through a feedback loop. Within this feedback loop, phase/frequency detector 102 compares the frequency and phase between reference clock 116 and divided clock 114. It then generates output signals that contain information related to the frequency and phase difference between the two input signals. The outputs of phase/frequency detector 102 pass through charge pump 104 and loop filter 106, and then into a control input of voltage-controlled oscillator 108. Voltage-controlled oscillator 108 generates output clock frequency 112 based on this control the input voltage. Frequency divider 110 then divides output clock frequency 112 and subsequently outputs divided clock 114. Through this feedback mechanism the phase and frequency between reference clock 116 and divided clock 114 becomes substantially equal after some time that is inversely proportional to the bandwidth of the feedback loop. Note that frequency divider 110 is set so that output clock frequency 112 is a multiple of reference clock frequency 116. For instance, if reference clock 116 is 100 Mhz and output clock frequency 112 is 1 GHz, frequency divider 110 divides output clock frequency 112 by a factor of 10 so that divided clock 114 is 100 Mhz.
Unfortunately, PLL design is becoming more difficult. As transistors become smaller, the supply voltages are being reduced, which reduces the headroom over the threshold voltage. Furthermore, modern high-performance systems are using high frequency clock signals in the multi-GHz range; these high frequencies reduce the tolerance for clock jitter and phase error.
FIG. 2A presents a block diagram of a typical (simplified) charge pump in a PLL. Note that there is a current mismatch between current flowing through pull-up network 200 and through pull-down network 202, which leads to charge build-up on capacitor 204 of loop filter 206 even if the phase and frequency difference is zero. This build-up, in turn, causes a shift in frequency and results in undesired phase error and jitter at the clock output.
FIG. 2B presents a current-versus-voltage plot of typical charge pump. In FIG. 2B, load-line plots of pull-up network current 208 and pull-down network current 210 are shown. Pull-up network current 208 intersects with pull-down network current 210 at operating point 216. At all other operating voltages (VFILTER), there is a mismatch in those currents. For instance, current mismatch 212 or current mismatch 214 can occur if the charge pump operates at filter voltage 218 or filter voltage 220, respectively.
FIG. 2C presents a current-versus-voltage curve of an ideal charge pump. In FIG. 2C, pull-up network current 222 and pull-down network current 224 are horizontal lines on the current-versus-voltage plot and intersect across a wide range of filter voltages. Note that the horizontal portions of the ideal curves would be directly on top of each other, but they are shown here with a small gap to illustrate the separate curves. Because an ideal charge pump is not feasible using existing technologies, the most common solution to mitigate the current mismatch problem is to cascode the current sources to boost the output impedances. Boosting the output impedances flattens the current-versus-voltage curves, thereby minimizing the current mismatch. However, boosting the output impedances reduces the output voltage swing of the charge pump. Furthermore, with sub-one-Volt power supplies, cascoding is no longer feasible because it reduces the voltage headroom for the transistors in the pull-up network and the pull-down network. This pushes the transistors out of the ideal operating range and reduces the output impedance of the pull-up network and the pull-down network.
Hence, what is needed is an apparatus for minimizing phase error and jitter in a phase-locked loop without the problems described above.